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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. mos integrated circuit mc-4564ec726 64 m-word by 72-bit synchronous dynamic ram module registered type data sheet document no. e0070n10 (1st edition) (previous no. m14460ej3v0ds00) date published january 2001 cp (k) printed in japan elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. description the mc-4564ec726 is a 67,108,864 words by 72 bits synchronous dynamic ram module on which 36 pieces of 128 m sdram: pd45128441 are assembled. these modules provide high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features ? 67,108,864 words by 72 bits organization (ecc type) ? clock frequency and access time from clk part number /cas latency clock frequency access time from clk module type (max.) (max.) mc-4564ec726efb-a80 cl = 3 125 mhz 6 ns pc100 registered dimm cl = 2 100 mhz 6 ns rev. 1.2 compliant mc-4564ec726efb-a10 cl = 3 100 mhz 6 ns cl = 2 77 mhz 7 ns MC-4564EC726PFB-A80 cl = 3 125 mhz 6 ns cl = 2 100 mhz 6 ns mc-4564ec726pfb-a10 cl = 3 100 mhz 6 ns cl = 2 77 mhz 7 ns mc-4564ec726xfb-a80 cl = 3 125 mhz 6 ns cl = 2 100 mhz 6 ns mc-4564ec726xfb-a10 cl = 3 100 mhz 6 ns cl = 2 77 mhz 7 ns ? fully synchronous dynamic ram, with all signals referenced to a positive clock edge ? pulsed interface ? possible to assert random column address in every cycle ? quad internal banks controlled by ba0 and ba1 (bank select) ? programmable burst-length (1, 2, 4, 8 and full page) ? programmable wrap sequence (sequential / interleave) ? programmable /cas latency (2, 3)
data sheet e0070n10 2 mc-4564ec726 ? automatic precharge and controlled precharge ? cbr (auto) refresh and self refresh ? all dqs have 10 ? 10 % of series resistor ? single 3.3 v 0.3 v power supply ? lvttl compatible ? 4,096 refresh cycles / 64 ms ? burst termination by burst stop command and precharge command ? 168-pin dual in-line memory module (pin pitch = 1.27 mm) ? registered type ? serial pd ? stacked monolithic technology ordering information part number clock frequency (max.) package mounted devices mc-4564ec726efb-a80 125 mhz 168-pin dual in-line memory module 36 pieces of pd45128441g5 (rev. e) mc-4564ec726efb-a10 100 mhz (socket type) (10.16 mm (400) tsop (ii)) MC-4564EC726PFB-A80 125 mhz edge connector: gold plated 36 pieces of pd45128441g5 (rev. p) mc-4564ec726pfb-a10 100 mhz 43.18 mm height (10.16 mm (400) tsop (ii)) mc-4564ec726xfb-a80 125 mhz 36 pieces of pd45128441g5 (rev. x) mc-4564ec726xfb-a10 100 mhz (10.16 mm (400) tsop (ii))
data sheet e0070n10 3 mc-4564ec726 pin configuration 168-pin dual in-line memory module socket type (edge connector: gold plated) 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 v ss dq32 dq33 dq34 dq35 vcc dq36 dq37 dq38 dq39 dq40 v ss dq41 dq42 dq43 dq44 dq45 vcc cb5 v ss nc nc vcc /cas dqmb4 dqmb5 /cs1 /ras v ss a1 a3 a5 a7 a9 ba0 (a13) a11 vcc clk1 nc v ss cke0 /cs3 dqmb6 dqmb7 nc vcc nc nc cb6 cb7 v ss dq48 dq49 dq50 dq51 vcc dq52 nc nc rege v ss dq53 dq54 dq55 v ss dq56 dq57 dq58 dq59 vcc dq60 dq61 dq62 dq63 v ss clk3 nc sa0 sa1 sa2 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 v ss dq0 dq1 dq2 dq3 vcc dq4 dq5 dq6 dq7 dq8 v ss dq9 dq10 dq11 dq12 dq13 vcc dq14 dq15 cb0 cb1 v ss nc nc vcc /we dqmb0 dqmb1 /cs0 nc v ss a0 a2 a4 a6 a8 a10 ba1(a12) vcc vcc clk0 v ss nc /cs2 dqmb2 dqmb3 nc vcc nc nc cb2 cb3 v ss dq16 dq17 dq18 dq19 vcc dq20 nc nc nc v ss dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 vcc dq28 dq29 dq30 dq31 v ss clk2 nc wp sda scl vcc dq46 dq47 cb4 /xxx indicates active low signal. a0 - a11 : address inputs [row: a0 - a11, column : a0 - a9, a11] ba0 (a13), ba1 (a12) : sdram bank select dq0 - dq63, cb0 - cb7 : data inputs/outputs clk0 - clk3 : clock input cke0 : clock enable input wp : write protect /cs0 - /cs3 : chip select input /ras : row address strobe /cas : column address strobe /we : write enable dqmb0 - dqmb7 : dq mask enable sa0 - sa2 : address input for eeprom sda : serial data i/o for pd scl : clock input for pd v cc : power supply v ss : ground rege : register / buffer enable nc : no connection
data sheet e0070n10 4 mc-4564ec726 block diagram (1/2) d0 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d18 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs rdqmb0 dq 3 dq 2 dq 1 dq 0 d9 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d27 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs rdqmb4 dq32 dq33 dq34 dq35 d2 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d20 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs rdqmb1 dq11 dq10 dq 9 dq 8 d11 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d29 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs rdqmb5 dq40 dq41 dq42 dq43 d1 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d19 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs dq 7 dq 6 dq 5 dq 4 d10 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d28 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs dq36 dq37 dq38 dq39 d3 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d21 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs dq15 dq14 dq13 dq12 d12 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d30 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs dq44 dq45 dq46 dq47 d4 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d22 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs cb 3 cb 2 cb 1 cb 0 d13 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d31 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs cb 4 cb 5 cb 6 cb 7 /rcs0 /rcs1 d5 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d23 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs rdqmb2 dq19 dq18 dq17 dq16 d14 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d32 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs rdqmb6 dq48 dq49 dq50 dq51 d7 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d25 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs rdqmb3 dq27 dq26 dq25 dq24 d16 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d34 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs rdqmb7 dq56 dq57 dq58 dq59 d6 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d24 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs dq23 dq22 dq21 dq20 d15 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d33 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs dq52 dq53 dq54 dq55 d8 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d26 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs dq31 dq30 dq29 dq28 d17 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d35 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs dq60 dq61 dq62 dq63 /rcs2 /rcs3 v cc d0 - d35, register1 - register3, pll d0 - d35, register1 - register3, pll c clk1 - clk3 12 pf 10 ? serial pd scl sda a0 a1 a2 sa0 sa1 sa2 wp 47 k ? clk0 pll clk: d0, d18, d9, d27 clk: d1, d19, d10, d28 clk: d2, d20, d11, d29 clk: d3, d21, d12, d30 clk: d4, d22, d13, d31 clk: d5, d23, d14, d32 clk: d6, d24, d15, d33 clk: d7, d25, d16, d34 clk: d8, d26, d17, d35 clk: register1- register3 10 ? v ss
data sheet e0070n10 5 mc-4564ec726 (2/2) register 1 a1 a3 a5 a7 a9 /ras /cas ba0 /cs1 dqmb4 dqmb5 rege r1a1: d0-d4, d9-d12, d18-d22, d27-d30 r2a1: d5-d8, d13-d17, d23-d26, d31-d35 r1a3: d0-d4, d9-d12, d18-d22, d27-d30 r2a3: d5-d8, d13-d17, d23-d26, d31-d35 r1a5: d0-d4, d9-d12, d18-d22, d27-d30 r2a5: d5-d8, d13-d17, d23-d26, d31-d35 r1a7: d0-d4, d9-d12, d18-d22, d27-d30 r2a7: d5-d8, d13-d17, d23-d26, d31-d35 r1a9: d0-d4, d9-d12, d18-d22, d27-d30 r2a9: d5-d8, d13-d17, d23-d26, d31-d35 r1ras: d0-d4, d9-d12, d18-d22, d27-d30 r2ras: d5-d8, d13-d17, d23-d26, d31-d35 r1cas: d0-d4, d9-d12, d18-d22, d27-d30 r2cas: d5-d8, d13-d17, d23-d26, d31-d35 r1ba0: d0-d4, d9-d12, d18-d22, d27-d30 rcs1 rdqmb4 rdqmb5 /le register 2 a0 a2 a4 a6 a8 a10 /we ba0 /cs0 dqmb0 dqmb1 r1a0: d0-d4, d9-d12, d18-d22, d27-d30 r2a0: d5-d8, d13-d17, d23-d26, d31-d35 r1a2: d0-d4, d9-d12, d18-d22, d27-d30 r2a2: d5-d8, d13-d17, d23-d26, d31-d35 r1a4: d0-d4, d9-d12, d18-d22, d27-d30 r2a4: d5-d8, d13-d17, d23-d26, d31-d35 r1a6: d0-d4, d9-d12, d18-d22, d27-d30 r2a6: d5-d8, d13-d17, d23-d26, d31-d35 r1a8: d0-d4, d9-d12, d18-d22, d27-d30 r2a8: d5-d8, d13-d17, d23-d26, d31-d35 r1a10: d0-d4, d9-d12, d18-d22, d27-d30 r2a10: d5-d8, d13-d17, d23-d26, d31-d35 r1we: d0-d4, d9-d12, d18-d22, d27-d30 r2we: d5-d8, d13-d17, d23-d26, d31-d35 r2ba0: d5-d8, d13-d17, d23-d26, d31-d35 rcs0 rdqmb4 rdqmb5 /le register 3 a11 ba1 cke0 /cs2 /cs3 dqmb2 dqmb3 dqmb6 dqmb7 r1a11: d0-d4, d9-d12, d18-d22, d27-d30 r2a11: d5-d8, d13-d17, d23-d26, d31-d35 r1ba1: d0-d4, d9-d12, d18-d22, d27-d30 r2ba1: d5-d8, d13-d17, d23-d26, d31-d35 r1cke0: d0-d2, d9-d10, d18-d20, d27-d28 r2cke0: d5-d6, d14-d15, d23-d24, d32-d33 r3cke0: d3-d4, d11-d13, d21-d22, d29-d31 r4cke0: d7-d8, d16-d17, d23-d24, d34-d35 rcs2 rcs3 rdqmb2 rdqmb3 rdqmb6 rdqmb7 /le 10 k ? remarks 1. the value of all resistors of dqs is 10 ? . 2. d0 C d35: pd45128441 (8m words 4 bits 4 banks) 3. rege v il : buffer mode rege v ih : register mode 4. register: hd74alvc16835 pll: hd74cdc2510b
data sheet e0070n10 6 mc-4564ec726 electrical specifications ? all voltages are referenced to v ss (gnd). ? after power up, wait more than 1 ms and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc C0.5 to +4.6 v voltage on input pin relative to gnd v t C0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 40 w operating ambient temperature t a 0 to 70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il C0.3 +0.8 v operating ambient temperature t a 0 70 c capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a11, ba0 (a13), ba1 (a12), /ras, /cas, /we tbd tbd pf c i2 clk0 tbd tbd c i3 cke0 tbd tbd c i4 /cs0 - /cs3 tbd tbd c i5 dqmb0 - dqmb7 tbd tbd data input/output capacitance c i/o dq0 - dq63, cb0 - cb7 tbd tbd pf
data sheet e0070n10 7 mc-4564ec726 dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition grade min. max. unit notes operating current i cc1 burst length = 1 /cas latency = 2 -a80 2,640 ma 1 t rc t rc (min.) , i o = 0 ma -a10 2,640 /cas latency = 3 -a80 2,640 -a10 2,640 precharge standby current in i cc2 p cke v il (max.) , t ck = 15 ns 286 ma power down mode i cc2 ps cke v il (max.) , t ck = 116 precharge standby current in i cc2 n cke v ih (min.) , t ck = 15 ns, /cs v ih (min.) , 970 ma non power down mode input signals are changed one time during 30 ns. i cc2 ns cke v ih (min.) , t ck = , 368 input signals are stable. active standby current in i cc3 p cke v il (max.) , t ck = 15 ns 430 ma power down mode i cc3 ps cke v il (max.) , t ck = 224 active standby current in i cc3 n cke v ih (min.) , t ck = 15 ns, /cs v ih (min.) , 1,330 ma non power down mode input signals are changed one time during 30 ns. i cc3 ns cke v ih (min.) , t ck = , 800 input signals are stable. operating current i cc4 t ck t ck (min.) , i o = 0 ma /cas latency = 2 -a80 2,730 ma 2 (burst mode) -a10 2,370 /cas latency = 3 -a80 3,180 -a10 2,820 cbr (auto) refresh current i cc5 t rc t rc (min.) /cas latency = 2 -a80 4,980 ma 3 -a10 4,980 /cas latency = 3 -a80 4,980 -a10 4,980 self refresh current i cc6 cke 0.2 v 322 ma input leakage current i i (l) v i = 0 to 3.6 v, all other pins not under test = 0 v C20 +20 a input leakage current (cke0) C40 +40 input leakage current (/cs0-/cs3, dqmb0-dqmb7) C10 +10 output leakage current i o (l) d out is disabled, v o = 0 to 3.6 v C3 +3 a high level output voltage v oh i o = C4.0 ma 2.4 v low level output voltage v ol i o = +4.0 ma 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck (min.) . 2 . i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck (min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck (min.) .
data sheet e0070n10 8 mc-4564ec726 ac characteristics (recommended operating conditions unless otherwise noted) test conditions parameter value unit ac high level input voltage / low level input voltage 2.4 / 0.4 v input timing measurement reference level 1.4 v transition time (input rise and fall time) 1 ns output timing measurement reference level 1.4 v t ck t ch t cl 2.4 v 1.4 v 0.4 v clk 2.4 v 1.4 v 0.4 v input t setup t hold output t ac t oh
data sheet e0070n10 9 mc-4564ec726 synchronous characteristics parameter symbol -a80 -a10 unit note min. max. min. max. clock cycle time /cas latency = 3 t ck3 8 (125 mhz) 10 (100 mhz) ns /cas latency = 2 t ck2 10 (100 mhz) 13 (77 mhz) ns access time from clk /cas latency = 3 t ac3 6 6 ns 1 /cas latency = 2 t ac2 6 7 ns 1 input clock frequency 50 125 50 100 mhz input clk duty cycle 40 60 40 60 % data-out hold time /cas latency = 3 t oh3 3 3 ns 1 /cas latency = 2 t oh2 3 3 ns 1 data-out low-impedance time t lz 0 0 ns data-out high- impedance time /cas latency = 3 t hz3 3 6 3 6 ns /cas latency = 2 t hz2 3 6 3 7 ns data-in setup time t ds 2 2 ns data-in hold time t dh 1 1 ns address setup time t as 2 2 ns address hold time t ah 1 1 ns cke setup time t cks 2 2 ns cke hold time t ckh 1 1 ns cke setup time (power down exit) t cksp 2 2 ns command (/cs0 - /cs3, /ras, /cas, /we, t cms 2 2 ns dqmb0 - dqmb7) setup time command (/cs0 - /cs3, /ras, /cas, /we, t cmh 1 1 ns dqmb0 - dqmb7) hold time note 1. output load output z = 50 ? 50 pf remark these specifications are applied to the monolithic device.
data sheet e0070n10 10 mc-4564ec726 asynchronous characteristics parameter symbol -a80 -a10 unit note min. max. min. max. act to ref/act command period (operation) t rc 70 70 ns ref to ref/act command period (refresh) t rc1 70 78 ns act to pre command period t ras 48 120,000 50 120,000 ns pre to act command period t rp 20 20 ns delay time act to read/write command t rcd 20 20 ns act(one) to act(another) command period t rrd 16 20 ns data-in to pre command period t dpl ? 1clk+8 ? 1clk+10 ns data-in to act(ref) command /cas latency = 3 t dal3 20 20 ns period (auto precharge) /cas latency = 2 t dal2 20 20 ns mode register set cycle time t rsc 2 2 clk transition time t t 0.5 30 1 30 ns refresh time (4,096 refresh cycles) t ref 64 64 ms
data sheet e0070n10 11 mc-4564ec726 serial pd (1/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 defines the number of bytes written into serial pd memory 80h 1 0 0 0 0 0 0 0 128 bytes 1 total number of bytes of serial pd memory 08h 0 0 0 0 1 0 0 0 256 bytes 2 fundamental memory type 04h 0 0 0 0 0 1 0 0 sdram 3 number of rows 0ch 0 0 0 0 1 1 0 0 12 rows 4 number of columns 0bh 0 0 0 0 1 0 1 1 11 columns 5 number of banks 02h 0 0 0 0 0 0 1 0 2 bank 6 data width 48h 0 1 0 0 1 0 0 0 72 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface 01h 0 0 0 0 0 0 0 1 lvttl 9 cl = 3 cycle time -a80 80h 1 0 0 0 0 0 0 0 8 ns -a10 a0h 1 0 1 0 0 0 0 0 10 ns 10 cl = 3 access time -a80 60h 0 1 1 0 0 0 0 0 6 ns -a10 60h 0 1 1 0 0 0 0 0 6 ns 11 dimm configuration type 02h 0 0 0 0 0 0 1 0 ecc 12 refresh rate/type 80h 1 0 0 0 0 0 0 0 normal 13 sdram width 04h 0 0 0 0 0 1 0 0 x4 14 error checking sdram width 04h 0 0 0 0 0 1 0 0 x4 15 minimum clock delay 01h 0 0 0 0 0 0 0 1 1 clock 16 burst length supported 8fh 1 0 0 0 1 1 1 1 1, 2, 4, 8, f 17 number of banks on each sdram 04h 0 0 0 0 0 1 0 0 4 banks 18 /cas latency supported 06h 0 0 0 0 0 1 1 0 2, 3 19 /cs latency supported 01h 0 0 0 0 0 0 0 1 0 20 /we latency supported 01h 0 0 0 0 0 0 0 1 0 21 sdram module attributes 1fh 0 0 0 1 1 1 1 1 registered 22 sdram device attributes : general 0eh 0 0 0 0 1 1 1 0 23 cl = 2 cycle time -a80 a0h 1 0 1 0 0 0 0 0 10 ns -a10 d0h 1 1 0 1 0 0 0 0 13 ns 24 cl = 2 access time -a80 60h 0 1 1 0 0 0 0 0 6 ns -a10 70h 0 1 1 1 0 0 0 0 7 ns 25-26 00h 0 0 0 0 0 0 0 0 27 t rp(min.) -a80 14h 0 0 0 1 0 1 0 0 20 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns 28 t rrd(min.) -a80 10h 0 0 0 1 0 0 0 0 16 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns 29 t rcd(min.) -a80 14h 0 0 0 1 0 1 0 0 20 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns 30 t ras(min.) -a80 30h 0 0 1 1 0 0 0 0 48 ns -a10 32h 0 0 1 1 0 0 1 0 50 ns 31 module bank density 40h 0 1 0 0 0 0 0 0 256m bytes
data sheet e0070n10 12 mc-4564ec726 (2/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 32 command and address signal input setup time 20h 0 0 1 0 0 0 0 0 2 ns 33 command and address signal input hold time 10h 0 0 0 1 0 0 0 0 1 ns 34 data signal input setup time 20h 0 0 1 0 0 0 0 0 2 ns 35 data signal input hold time 10h 0 0 0 1 0 0 0 0 1 ns 36-61 00h 0 0 0 0 0 0 0 0 62 spd revision 12h 0 0 0 1 0 0 1 0 1.2 a 63 checksum for bytes 0 - 62 -a80 3bh 0 0 1 1 1 0 1 1 -a10 a1h 1 0 1 0 0 0 0 1 64-71 manufactures jedec id code 72 manufacturing location 73-90 manufactures p/n 91 revision code 93-94 manufacturing date 95-98 assembly serial number 99-125 mfg specific 126 intel specification frequency 64h 0 1 1 0 0 1 0 0 100 mhz 127 intel specification /cas -a80 87h 1 0 0 0 0 1 1 1 latency support -a10 85h 1 0 0 0 0 1 0 1 timing chart refer to the pd45128441, 45128841, 45128163 data sheet (e0031n).
data sheet e0070n10 13 mc-4564ec726 package drawing m1 (area b) y m2 (area a) a d g i q u t detail of a part x v (optional holes) s n w j r b z 168-pin dual in-line module (socket type) item millimeters a b 133.35 133.35 0.13 6.35 d d1 a1 11.43 c 36.83 2.0 d2 3.125 e 54.61 g 6.35 i 8.89 j 24.495 h 1.27 (t.p.) l 42.18 23.40 m1 m2 k 17.78 m 43.18 0.13 19.78 n 6.35 max. p 1.0 q r2.0 s 3.0 t 1.27 0.1 r 4.0 0.10 u 4.0 min. v 0.2 0.15 x 2.54 0.10 y 3.0 min. z 3.0 min. w 1.0 0.05 m168s-50a112 detail of b part d2 d1 p a (area b) a1 (area a) l m e k h c b
data sheet e0070n10 14 mc-4564ec726 [memo]
data sheet e0070n10 15 mc-4564ec726 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
mc-4564ec726 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. m8e 00. 4 the information in this document is current as of september, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of elpida's data sheets or data books, etc., for the most up-to-date specifications of elpida semiconductor products. not all products and/or types are available in every country. please check with an elpida memory, inc. for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of elpida. elpida assumes no responsibility for any errors that may appear in this document. elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of elpida semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while elpida endeavours to enhance the quality, reliability and safety of elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. elpida semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of elpida semiconductor products is "standard" unless otherwise expressly specified in elpida's data sheets or data books, etc. if customers wish to use elpida semiconductor products in applications not intended by elpida, they must contact an elpida memory, inc. in advance to determine elpida's willingness to support a given application. (note) (1) "elpida" as used in this statement means elpida memory, inc. and also includes its majority-owned subsidiaries. (2) "elpida semiconductor products" means any semiconductor product developed or manufactured by or for elpida (as defined above). ? ? ? ? ? ?

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